View MT48LC16M16LF_1632870.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 09005aef80737ef7 256mbx16_1.fm - rev. e 4/04 en 1 ?2002 micron technology, inc. all rights reserved. 256mb: x16 mobile sdram preliminary ? mobile sdram MT48LC16M16LF, mt48g16m16lf, mt48v16m16lf 4 meg x 16 x 4 banks features ? fully synchronous; all signals registered on positive edge of system clock internal pipelined operat ion; column address can be changed every clock cycle internal banks for hiding row access/precharge programmable burst lengths: 1, 2, 4, 8, or full page auto precharge, includes concurrent auto precharge and auto refresh modes self refresh mode 64ms, 8,192-cycle refresh lvttl-compatible inputs and outputs low voltage power supply temperature compensated self refresh (tcsr) option marking v dd /v dd q 3.3v/3.3v lc 3.0v/3.0v g 2.5v/2.5v-1.8v v configurations 16 meg x 16 (4 meg x 16 x 4 banks) 16m16 plastic packages - ocpl 54-pin tsop (400 mil) 1 note: 1. contact factory for availability. tg 54-pin tsop (400 mil) lead-free 1 p 54-ball vfbga (8mm x 14mm) 2 2. due to space limitations, fbga-packaged components have an abbreviated part marking that is different from the part number. for a quick conversion of an fbga code, see the fbga part marking decoder on the micron web site, www.micron.com/decoder . fg 54-ball vfbga (8mm x 14mm) lead-free 2 bg 54-ball vfbga (11mm x 8mm) 2 f8 54-ball vfbga (11mm x 8mm) lead-free 2 b8 timing (cycle time) 7.5ns @ cl = 3 (133mhz) -75 8.0ns @ cl = 3 (125 mhz) -8 9.6ns @ cl = 3 (104 mhz) -10 self refresh standard none operating temperature commercial (0 o c to + 70 o c) none extended (-25 o c to + 75 o c) xt industrial (-40 o c to + 85 o c) it table 1: key timing parameters speed grade clock frequency access time 1 note: 1. *cl = cas (read) latency setup time hold time cl=1 cl=2 cl=3 -75 133 mhz - - 5.4ns 1.5ns 0.8ns -8 125 mhz - - 7ns 2.5ns 1.0ns -10 104 mhz - 8ns 7ns 2.5ns 1.0ns -75 104 mhz - 6ns - 1.5ns 1.0ns -8 104 mhz - 8ns - 2.5ns 1.0ns -10 83 mhz - 8ns - 2.5ns 1.0ns -8 50 mhz 19ns - - 2.5ns 1.0ns a b c d e f g h j 1 2 3 4 5 6 7 8 v ss dq14 dq12 dq10 dq8 udqm a12 a8 v ss dq15 dq13 dq11 dq9 nc clk a11 a7 a5 v ss q v dd q v ss q v dd q v ss cke a9 a6 a4 v dd q v ss q v dd q v ss q v dd cas\ ba0 a0 a3 dq0 dq2 dq4 dq6 ldqm ras\ ba1 a1 a2 v dd dq1 dq3 dq5 dq7 we\ cs\ a10 vdd 9 figure 1: ball assignment (top view) 54-ball vfbga 16 meg x 16 configuration 4 meg x 16 x 4 banks refresh count 8k row addressing 8k (a0-a12) bank addressing 4 (ba0, ba1) column addressing 512 (a0-a8)
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16toc.fm - rev. e 4/04 en 2 ?2002 micron technology, inc. all rights reserved. table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 write burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 low power extended mode register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 temperature compensated self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 driver strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 command inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 no operation (nop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 load mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 bank/row activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 clock suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 burst read/single write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 concurrent auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 data sheet designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16lof.fm - rev. e 4/04 en 3 ?2002 micron technology, inc. all rights reserved. list of figures figure 1: ball assignment (top view) 54-ba ll vfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: pin assignment (top view) 54-pin tsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 3: 256mb mobile sdram part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 4: functional block diagram 16 meg x 16 sdram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 figure 5: mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 6: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 7: low power extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 8: activating a specific row in a specific bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 9: example: meeting t rcd (min) when 2 < t rcd (min)/ t ck 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 10: read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 11: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 12: consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 13: random read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 14: read to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 15: read to write with extra clock cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 16: read to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 17: terminating a read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 18: write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 19: write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 20: write to write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 21: random write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 22: write to read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 23: write to precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 24: terminating a write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 25: precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 26: power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 27: clock suspend during write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 28: clock suspend during read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 29: read with auto precharge interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 30: read with auto precharge interrupted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 31: write with auto precharge interrupted by a read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 32: write with auto precharge interrupted by a write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 33: initialize and load mode register 1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 34: power-down mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 35: clock suspend mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 36: auto refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 figure 37: self refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 38: read ? without auto precharge1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 39: read ? with auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 40: single read ? without auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 41: single read ? with auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 42: alternating bank read accesses 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 43: read ? full-page burst 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 44: read ? dqm operation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 45: write ? wi thout auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 46: write ? wi th auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 47: single write ? without auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 48: single write ? with auto precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 49: alternating bank write accesses 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 50: write ? full-page burst 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 51: write ? dqm operation 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 52: 54-pin plastic tsopii (400 mil). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 53: vfbga 54-ball, 8mm x 14mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 54: vfbga 54-ball, 11mm x 8mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16lot.fm - rev. e 4/04 en 4 ?2002 micron technology, inc. all rights reserved. list of tables table 1: key timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: ball/pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 3: burst definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 table 4: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 5: truth table - commands and dqm operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 6: truth table ? cke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 7: truth table ? current state bank n , command to bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 8: truth table ? current state bank n, command to bank m. . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 9: dc electrical characteristics and operating conditions (lc version). . . . . . . . . . . . . . . . . . . . . . . . . .3 4 table 10: dc electrical characteristics and operating conditions (g version). . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 11: dc electrical characteristics and operating conditions (v version) . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 12: capacitance - vfbga. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 13: capacitance - tsop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 14: electrical characteristics and re commended ac operating conditions . . . . . . . . . . . . . . . . . . . . . . .36 table 15: ac functional characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 16: i dd specifications and conditions - lc, g, v versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 17: i dd 7 self refresh current options - lc, g, v versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 5 ?2002 micron technology, inc. all rights reserved. figure 2: pin assignment (top view) 54-pin tsop v dd dq0 v dd q dq1 dq2 vssq dq3 dq4 v dd q dq5 dq6 vssq dq7 v dd dqml we# cas# ras# cs# ba0 ba1 a10 a0 a1 a2 a3 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 vss dq15 vssq dq14 dq13 v dd q dq12 dq11 vssq dq10 dq9 v dd q dq8 vss nc dqmh clk cke a12 a11 a9 a8 a7 a6 a5 a4 vss x16 x16
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 6 ?2002 micron technology, inc. all rights reserved. figure 3: 256m b mobile sdram part numbering note: not all speed grade and configurations avail- able, contact factory for availability. general description the 256mb mobile sdram is a high-speed cmos, dynamic random-access memory containing 268,435,456 bits. it is internally configured as a quad- bank dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits. read and write accesses to the sdram are burst ori- ented; accesses start at a selected location and con- tinue for a programmed number of locations in a programmed sequence. accesses begin with the regis- tration of an active command, which is then fol- lowed by a read or write command. the address bits registered coincident with the active command are used to select the bank and row to be accessed (a13 and a14 select the bank; a0?a12 select the row). the address bits registered coincident with the read or write command are used to select the starting col- umn location for the burst access. the sdram provides for programmable read or write burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the 256mb mobile sdram uses an internal pipe- lined architecture to achieve high-speed operation. this architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high- speed, random-access operation. the 256mb sdram is designed to operate in 3.3v or 3.0v or 2.5v memory systems. an auto refresh mode is provided, along with a power-saving, power-down mode. all inputs and outputs are lvttl-compatible. sdrams offer substantial advances in dram oper- ating performance, including the ability to synchro- nously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. configuration micron sdram mt48 mobile configuration v dd / v dd q package speed temp speed grade t ck = 7.5ns t ck = 8.0ns t ck = 9.6ns -75 -8 -10 it xt operating temp commercial industrial temp extended temp example part number: m t48v16m16lftg-75 it tg p fg bg f8 b8 package 400-mil tsop 400-mil tsop (lead-free) 8x14 vfbga 8x14 vfbga (lead-free) 11x8 vfbga 11x8 vfbga (lead-free) lc g v v dd /v dd q 3.3v/3.3v 3.0v/3.0v 2.5v/2.5v - 1.8v configuration 16 meg x 16 16m16lf -
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 7 ?2002 micron technology, inc. all rights reserved. figure 4: functional bloc k diagram 16 meg x 16 sdram 13 ras# cas# row- address mux clk cs# we# cke control logic column- address counter/ latch mode register 9 command decode a0-a12, ba0, ba1 dqml, dqmh 13 address register 15 512 (x16) 8192 i/o gating dqm mask logic read data latch write drivers column decoder bank0 memory array (8,192 x 512 x 16) bank0 row- address latch & decoder 8192 sense amplifiers bank control logic dq0- dq15 16 16 data input register data output register 16 12 bank1 bank2 bank3 13 9 2 2 2 2 refresh counter
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 8 ?2002 micron technology, inc. all rights reserved. table 2: ball/pin descriptions 54-ball vfbga 54-pin tsop symbol type description f2 38 clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and co ntrols the outp ut registers. f3 37 cke input clock enable: cke activates (high) and deactivates (low) the clk signal. deactivating the clock provides precharge power-down and selfrefresh operation (all ba nks idle), active power-down (row active in any bank) or cloc k suspend operation (burst/access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke becomes asynchronous until after exiting th e same mode. the input buffers, including clk, are disabled duri ng power-down and self refresh modes, providing low standby power. cke may be tied high. g9 19 cs# input chip select: cs# enables (registere d low) and disables (registered high) the command decoder. all co mmands are masked when cs# is registered high. cs# provides fo r external bank selection on systems with multiple banks. cs# is considered part of the command code. f7, f8, f9 17, 18, 16 cas#, ras#, we# input command inputs: cas#, ras#, and w e# (along with cs#) define the command being entered. e8, f1 15, 39 dqml, dqmh input input/output mask: dqm is sampled high and is an input mask signal for write accesses and an output enable signal for read accesses. input data is masked du ring a write cycle. the output buffers are placed in a high-z state (two-clock latenc y) when during a read cycle. ldqm corresponds to dq0-dq7, udqm corresponds to dq8-dq15. ldqm and udqm are considered same state when referenced as dqm. g7, g8 20, 21 ba0, ba1 input bank address input(s): ba0 and ba1 define to which bank the active, read, write or precharge command is being applied. these pins also provide the op-c ode during a load mode register command h7, h8, j8, j7, j3, j2, h3, h2, h1, g3, h9, g2,g1 23-26, 29- 34, 22, 35, 36 a0-a12 input address inputs: a0-a12 are sample d during the active command (row address a0-a12) and read/write command (column- addressa0-a8; witha10 defining au to precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a prec harge command to determine if all banks are to be precharged (a10 high) or bank selected by ba0, ba1 (low). the address inputs also pr ovide the op-code during a load mode register command. a8, b9, b8, c9, c8, d9, d8, e9, e1, d2, d1, c2, c1, b2, b1, a2 2, 4, 5, 7, 8, 10, 11, 13, 42, 44, 45, 47, 48, 50, 51, 53 dq0-dq15 i/o data input/output: data bus e2, 40 nc - no connect: this pin should be left unconnected. a7, b3, c7, d3 3, 9, 43, 49 v dd q supply dq power: provide isolated power to dqs for improved noise immunity. a3, b7, c3, d7, 6, 12, 46, 52 v ss q supply dq ground: provide isolated ground to dqs for improved noise immunity. a9, e7, j9 1, 14, 27 v dd supply power supply: voltage dependant on option. a1, e3, j1 28, 41, 54 v ss supply ground.
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 9 ?2002 micron technology, inc. all rights reserved. functional description in general, the 256mb sdrams (4 meg x 16 x 4 banks) are quad-bank drams that operate at 3.3v, 3.0v, or 2.5v and include a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the 67,108,864-bit banks is orga- nized as 8,192 rows by 512 columns by 16 bits. read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a programmed number of lo cations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coin- cident with the active command are used to select the bank and row to be accessed (ba0 and ba1 select the bank, a0?a12 select the row). the address bits (a0? a8) registered coincident with the read or write command are used to select the starting column loca- tion for the burst access. prior to normal operation, the sdram must be ini- tialized. the following sections provide detailed infor- mation covering device initialization, register definition, command descriptions and device opera- tion. initialization sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined opera- tion. once power is applied to vdd and vddq (simul- taneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the sdram requires a 100s delay prior to issuing any command other than a command inhibit or nop. cke must be held high during the entire initialization period until the pre- charge command has been issued. starting at some point during this 100s peri od and continuing at least through the end of this period, command inhibit or nop commands should be applied. once the 100s delay has been satisfied with at least one command inhibit or nop command having been applied, a precha rge command should be applied. all banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. register definition mode register the mode register is used to define the specific mode of operation of th e sdram. this definition includes the selection of a burst length, a burst type, a cas latency, an operating mode and a write burst mode, as shown in figure 5 on page 10. the mode reg- ister is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0?m2 specify the burst length, m3 specifies the type of burst (sequential or inter- leaved), m4?m6 specify the cas latency, m7 and m8 specify the operating mode , m9 specifies the write burst mode, and m10, m11, and m12 should be set to zero. m13and m14 should be set to zero to prevent extended mode register. the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. vio- lating either of these requirements will result in unspecified operation. burst length read and write accesses to the sdram are burst ori- ented, with the burst length being programmable, as shown in figure 5. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. the full-page burst is used in conjunction with the burst terminate command to ge nerate arbitrary burst lengths. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1?a8 when the burst length is set to two; by a2?a8 when the burst length is set to four; and by a3?a8 when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full- page bursts wrap within the page if the boundary is reached.
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 10 ?2002 micron technology, inc. all rights reserved. burst type accesses within a given burst may be programmed to be either sequential or in terleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is deter- mined by the burst length, th e burst type and the start- ing column address, as shown in table 3. figure 5: mode register definition notes 1. for full-page accesses: y = 512. 2. for a burst length of two, a1-a8 select the block-of- two burst; a0 selects the st arting column within the block. 3. for a burst length of four , a2-a8 select the block-of- four burst; a0-a1 select the starting column within the block. 4. for a burst length of eight, a3-a8 select the block-of- eight burst; a0-a2 select th e starting co lumn within the block. 5. for a full-page burst, the full row is selected and a0-a8 select the starting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for a burst length of one, a0-a8 select the unique col- umn to be accessed, and mode register bit m3 is ignored. 14 10 m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved 1 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 op mode a10 a11 11 reserved* wb 0 1 write burst mode programmed burst length single location access m9 *should program m12, m11, m10 = ?0, 0, 0? to ensure compatibility with future devices. a12 ba0 13 12 ba1 0 0 table 3: burst definition burst length order of accesses within a burst starting column address ty pe = sequential ty pe = interleaved 2a0 00-1 0-1 11-0 1-0 4a1a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8a2a1a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (y) n = a0-a11/ 9/8 (location 0-y) cn, cn + 1, cn + 2 cn + 3, cn + 4... ?cn - 1, cn? not supported
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 11 ?2002 micron technology, inc. all rights reserved. cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. the dqs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the rele vant access times are met, the data will be valid by clock edge n + m. for example, assuming that the clock cycle time is such that all rele- vant access times are met, if a read command is regis- tered at t0 and the latency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in figure 6. figure 4 indi- cates the operating frequencies at which each cas latency setting can be used. figure 6: cas latency note: each read command may be to either bank. dqm is low. bl=4 reserved states should not be used as unknown operation or incompatibility with future versions may result. operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. write burst mode when m9 = 0, the burst length programmed via m0- m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (non- burst) accesses. clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 0 cycles cas latency = 1 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 1 cycle cas latency = 2 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read nop t7 x = 2 cycles cas latency = 3 don?t care transitioning data table 4: cas latency speed allowable operating frequency (mhz) cas latency = 1 cas latency = 2 cas latency = 3 - 75 - 104 133 - 8 50 104 125 - 10 40 83 104
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 12 ?2002 micron technology, inc. all rights reserved. figure 7: low power extended mode register note: 1. e14 and e13 (ba1 and ba0) must be ?1, 0? to select the low power extended mode register (vs. the base mode register). 2. not setting the low power extended mode regis- ter will result in the default values indicated. low power extended mode register the extended mode register controls the functions beyond those controlled by the mode register. these additional functions are special features of the mobile device. they include temperature compensated self refresh (tcsr), partial array self refresh (pasr) and drive strength. not programming the low power extended mode register upon initialization will result in the default settings for the low power features. the lpemr will default to tcsr = 85c, full drive strength and full array refresh.the lpemr will default to tcsr in temperature sensor mode (e4 and e3 = 0,0), full drive strength and full array refresh. the low power extended mode register is pro- grammed via the mode register set command (ba1=1,ba0=0) and retains the stored information until it is programmed again or the device loses power. the low power extended mode register must be programmed with e7 through e12 set to ?0.? the low power extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiat- ing any subsequent operation. violating these require- ments results in unspecified operation. temperature compensated self refresh temperature compensated self refresh allows the controller to program the refresh interval during self refresh mode, according to the case temperature of the mobile device. this allows great power savings during self refresh during most operating temper- ature ranges. every cell in the dram requires refreshing due to the capacitor losing its charge over time. the refresh rate is dependent on temperature. at higher tempera- tures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often. historically, during self refresh, the refresh rate has been set to accommodate the worst case, or high- est temperature range expected. thus, during ambient temperatures, the power con- sumed during refresh was unnecessarily high, because the refresh rate was set to accommodate the higher temperatures. setting e4 and e3, allow the dram to accommodate more specific temperature regions dur- ing self refresh. there are four temperature set- tings, which will vary the self refresh current according to the selected temperature. this selectable refresh rate will save power when the dram is operat- ing at normal temperatures. driver strength low power extended mode register bit e5 and e6 must be used to set the dq output drive strength. driver strength chosen should be load dependent. the lighter the load, the less driver strength that is needed for the outputs. maximum case temp e4 e3 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 low power extended mode register (ex) address bus 976543 8210 a10 a11 ba0 10 11 12 13 14 a12 set to 0 tcsr 1 0 all have to be set to "0" all have to be set to "0" ba1 85c 2 1 1 70c 0 0 45c 15c 0 1 1 0 ds driver strength full strength 2 half strength reserved reserved e6 e5 0 0 1 1 0 1 0 1 1
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 13 ?2002 micron technology, inc. all rights reserved. commands table 5 provides a quick reference of available com- mands. this is followed by a written description of each command. three additional truth tables appear following the operation section; these tables provide current state/next state information. note: 1. cke is high for all commands shown ex cept self refresh and deep power-down. 2. a0-a11 define the op-code written to the mo de register, and a12 should be driven low. 3. a0-a12 provide row address, and ba0, ba1 determine which bank is made active. 4. a0-a8 provide column address; a10 hi gh enables the auto precha rge feature (nonpersistent), while a10 low disables the auto precharge feature; ba0, ba1 determine which bank is being read from or written to. 5. a10 low: ba0, ba1 determine the bank being precharged. a10 high: all banks precharged and ba0, ba1 are ?don?t care.? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except for cke. 8. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay). 9. this command is burst terminate if cke is high, deep power-down if cke is low. table 5: truth table - commands and dqm operation (note: 1) name (function) cs# ras# cas# we# dqm addr dqs notes command inhibit (nop) h xxxx x x no operation (nop) l h h h x x x active (select bank and activate row) l l h h x bank/row x 3 read (select bank and column, and start read burst) l h l h l/h 8 bank/col x 4 write (select bank and column, and start write burst) l h l l l/h 8 bank/col valid 4 burst terminate or deep power-down l h h l x x active 9 precharge (deactivate row in bank or banks) l l h l x code x 5 auto refresh or self refresh (enter self refresh mode) ll lhx x x 6, 7 load mode register l l l l x op-code x 2 write enable/output enable x x x x l x active 8 write inhibit/output high-z x x x x h x high-z 8
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 14 ?2002 micron technology, inc. all rights reserved. command inhibit the command inhibit function prevents new commands from being executed by the sdram, regardless of whether the clk signal is enabled. the sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to perform a nop to an sdram which is selected (cs# is low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode register is loaded via inputs a0-a12 (ba1, ba0 should be driven low to prevent low power extended mode register.) see mode register heading in the register definition section. the load mode register command can only be issued when all banks are idle, and a subseq uent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a12 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a pre- charge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a8 selects the star ting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. read data appears on the dqs subject to the logic level on the dqm inputs two clocks earlier. if a given dqm signal was registered high, the corresponding dqs will be high-z two clocks later; if the dqm signal was regis- tered low, the dqs will provide valid data. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a8 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dqm input logic level appearing coincident with the data. if a given dqm signal is reg- istered low, the correspondin g data will be written to memory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column loca- tion. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. auto precharge auto precharge is a feature which performs the same individual-bank precharge function described above, without requiring an explicit com- mand. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst, except in the full-page burst mode, where auto precharge does not apply. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write com- mand. auto precharge ensures that the precharge is initi- ated at the earliest valid st age within a burst. the user must not issue another command to the same bank until the precharge time ( t rp) is completed. this is determined as if an explicit precharge command
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 15 ?2002 micron technology, inc. all rights reserved. was issued at the earliest possible time, as described for each burst type in the operation section of this data sheet. auto refresh auto refresh is used during normal operation of the sdram and is analogous to cas#-before-ras# (cbr) refresh in conventional drams. this com- mand is nonpersistent, so it must be issued each time a refresh is required. all active banks must be pre- charged prior to issuing an auto refresh com- mand. the auto refresh command should not be issued until the minimum t rp has been met after the precharge command as shown in the operations section. the addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during an auto refresh command. the 256mb sdram requires 8,192 auto refresh cycles every 64ms ( t ref), regardless of width option. providing a distributed auto refresh command every 7.81s will meet the refresh requirement and ensure that each row is refreshed. alternatively, 8,192 auto refresh commands can be issued in a burst at the minimum cycle rate ( t rfc), once every 64ms. self refresh the self refresh command can be used to retain data in the sdram, even if the rest of the system is powered down. when in the self refresh mode, the sdram retains data withou t external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). once the self refresh command is registered, all the inputs to the sdram become ?don?t care? with the exception of cke, which must remain low. once self refresh mode is engaged, the sdram pro- vides its own internal clocking, causing it to perform its own auto refresh cycles. the sdram must remain in self refresh mode for a minimum period equal to t ras and may remain in self refresh mode for an indefinite period beyond that. the procedure for exiting self refresh requires a sequence of commands. first, clk must be stable (sta- ble clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to cke going back high. once cke is high, the sdram must have nop commands issued (a minimum of two clocks) for t xsr because time is required for the com- pletion of any internal refresh in progress. upon exiting the self refresh mode, auto refresh commands must be issued every 7.81s or less as both self refresh and auto refresh utilize the row refresh counter.
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 16 ?2002 micron technology, inc. all rights reserved. operation bank/row activation before any read or write commands can be issued to a bank within the sdram, a row in that bank must be ?opened.? this is accomplished via the active command, which selects both the bank and the row to be activated shown in figure 8. after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specification of 20ns with a 125 mhz clock (8ns period) results in 2.5 clocks, rounded to 3. this is reflected in figure 9, which covers any case where 2 < t rcd (min)/ t ck 3. (the same procedure is used to convert other specification limits from time units to clock cycles.) a subsequent active command to a dif- ferent row in the same bank can only be issued after the previous active row has been ?closed? (pre- charged). the minimum time interval between succes- sive active commands to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access over- head. the minimum time interval between successive active commands to different banks is defined by t rrd. figure 8: activating a specific row in a specific bank figure 9: example: meeting t rcd (min) when 2 < t rcd (min)/ t ck 3 cs# we# cas# ras# cke clk a0-a12 row address don?t care high ba0, ba1 bank address clk t2 t1 t3 t0 t command nop active read or write t4 nop rcd don?t care
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 17 ?2002 micron technology, inc. all rights reserved. reads read bursts are initiated with a read command, as shown in figure 10. the starting column and bank addresses are pro- vided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is pre- charged at the completion of the burst. for the generic read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address will be available fol- lowing the cas latency after the read command. each subsequent data-out element will be valid by the next positive cl ock edge. figure 11 shows general tim- ing for each possible cas latency setting. figure 10: read command upon completion of a burst, assuming no other commands have been initiated, the dqs will go high- z. a full-page burst will continue until terminated. (at the end of the page, it will wrap to the start address and continue.) data from any read burst may be trun- cated with a subsequent read command, and data from a fixed-length read burst may be immediately followed by data from a read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. the new read command should be issued x cycles before the clock edge at which the last desired data ele- ment is valid, where x equals the cas latency minus one. figure 11: cas latency don?t care cs# we# cas# ras# cke clk column address a0-a8 a10 ba0,1 high enable auto precharge disable auto precharge bank address a9, a11, a12 clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop don?t care undefined clk dq t2 t1 t0 cas latency = 1 lz d out t oh t command nop read t ac clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 18 ?2002 micron technology, inc. all rights reserved. this is shown in figure 12 for cas latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. the 256mb sdram uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. a read command can be initi- ated on any clock cycle following a previous read command. full-speed random read accesses can be performed to the same bank, as shown in figure 13, or each subsequent read may be performed to a differ- ent bank. figure 12: consecutive read bursts figure 13: random read accesses note: each read command may be to either bank. dqm is low. data from any read burst may be truncated with a subsequent write command, and data from a fixed- length read burst may be immediately followed by data from a write command (subject to bus turn- around limitations). the wr ite burst may be initiated on the clock edge immediately following the last (or last desired) data element from the read burst, pro- vided that i/o contention can be avoided. in a given system design, there may be a possibility that the device driving the input data will go low-z before the sdram dqs go high-z. in this case, at least a single- cycle delay should occur between the last read data and the write command. the dqm input is used to avoid i/o contention, as shown in figures 9 and 10. the dqm signal must be asserted (high) at least two clocks prior to the write command (dqm latency is two clocks for output buff- clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 0 cycles cas latency = 1 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 1 cycle cas latency = 2 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read nop t7 x = 2 cycles cas latency = 3 don?t care transitioning data clk dq t2 t1 t4 t3 t6 t5 t0 command address read nop nop bank, col n don?t care d out n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop bank, col n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t0 command address read nop bank, col n d out a d out x d out m read read read bank, col a bank, col x bank, col m cas latency = 1 cas latency = 2 cas latency = 3 transitioning data
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 19 ?2002 micron technology, inc. all rights reserved. ers) to suppress data-out from the read. once the write command is registered, the dqs will go high-z (or remain high-z), regardless of the state of the dqm signal; provided the dqm was active on the clock just prior to the write command that truncated the read command. if not, the second write will be an invalid write. for example, if dqm was low during t4 in figure 15, then the writes at t5 and t7 would be valid, while the write at t6 would be invalid. the dqm signal must be de-asserted prior to the write command (dqm latency is zero clocks for input buffers) to ensure that the written data is not masked. figure 14 shows the case where the clock fre- quency allows for bus contention to be avoided with- out adding a nop cycle, and figure 15 shows the case where the additional nop is needed. figure 14: read to write note: a cas latency of three is used for illustration. the read command may be to any bank, and the write command may be to any bank. if a burst of one is used, then dqm is not required. figure 15: read to write with extra clock cycle note: a cas latency of three is used for illustration. the read command may be to any bank, and the write command may be to any bank. a fixed-length read burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto pr echarge was not activated), and a full-page burst may be truncated with a pre- charge command to the same bank. the pre- charge command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 16 on page 20, for each possible cas latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden dur- ing the access of the last data element(s). don?t care read nop nop write nop clk t2 t1 t4 t3 t0 dqm dq d out n command d in b address bank, col n bank, col b ds t hz t t ck transitioning data don?t care read nop nop nop nop dqm clk dq d out n t2 t1 t4 t3 t0 command address bank, col n write d in b bank, col b t5 ds t hz t transitioning data
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 20 ?2002 micron technology, inc. all rights reserved. figure 16: read to precharge note: dqm is low. in the case of a fixed-length burst being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvantage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length or full-page bursts. full-page read bursts can be truncated with the burst terminate command, and fixed-length read bursts may be truncated with a burst termi- nate command, provided that auto precharge was not activated. the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 17 for each possible cas latency; data element n + 3 is the last desired data element of a longer burst. clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank a , col n nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 bank a , row bank ( a or all) x = 0 cycles cas latency = 1 x = 1 cycle cas latency = 2 cas latency = 3 bank a , col n bank a , row bank ( a or all) bank a , col n bank a , row bank ( a or all) x = 2 cycles
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 21 ?2002 micron technology, inc. all rights reserved. figure 17: terminating a read burst note: 1. dqm is low. 2. burst length is full page. don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop x = 0 cycles cas latency = 1 x = 1 cycle cas latency = 2 cas latency = 3 x = 2 cycles transitioning data
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 22 ?2002 micron technology, inc. all rights reserved. writes write bursts are initiated with a write command, as shown in figure 18. the starting column and bank addresses are pro- vided with the write command, and auto precharge is either enabled or disabl ed for that access. if auto precharge is enabled, the row being accessed is pre- charged at the completion of the burst. for the generic write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element will be registered coincident with the write com- mand. subsequent data elements will be registered on each successive positive clock edge. upon completion of a fixed-length burst, assuming no other commands have been initiated, the dqs will remain high-z and any additional input data will be ignored as shown in figure 19. a full-page burst will continue until termi- nated. (at the end of the page, it will wrap to the start address and continue.) data for any write burst may be truncated with a subsequent write command, and data for a fixed-length write burst may be immedi- ately followed by data for a write command. the new write command can be issued on any clock following the previous write command, and the data provided coincident with the new command applies to the new command. an example is shown in figure 20. data n + 1 is either the last of a burs t of two or the last desired of a longer burst. the 256mb sdram uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. a write com- mand can be initiated on any clock cycle following a previous write command. full-speed random write accesses within a page can be performed to the same bank, as shown in figure 21, or each subsequent write may be performed to a different bank. figure 18: write command figure 19: write burst note: burst length = 2. dqm is low. figure 20: write to write note: dqm is low. each write command may be to any bank. cs# we# cas# ras# cke clk column address don?t care high enable auto precharge disable auto precharge bank address a0-a8: x16 a10 ba0,1 a9, a11,a12: x16 valid address clk dq d in n t2 t1 t3 t0 command address nop nop don?t care write d in n + 1 nop bank, col n clk dq t2 t1 t0 command address nop write write bank, col n bank, col b d in n d in n + 1 d in b note: dqm is low. each write command may be to any bank. don?t care transitioning data
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 23 ?2002 micron technology, inc. all rights reserved. data for any write burst may be truncated with a subsequent read command, and data for a fixed- length write burst may be immediately followed by a read command. once the read command is regis- tered, the data inputs will be ignored, and writes will not be executed. an example is shown in figure 22. data n + 1 is either the last of a burst of two or the last desired of a longer burst. data for a fixed-length write burst may be fol- lowed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not activated), and a full -page write burst may be truncated with a precharge command to the same bank. the precharge command should be issued t wr after the clock edge at which the last desired input data element is registered. the auto precharge mode requires a t wr of at least one clock plus time, regard- less of frequency. in addition, when truncating a write burst, the dqm signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the precharge command. an example is shown in figure 23. data n + 1 is either the last of a burst of two or the last desired of a longer burst. following the precharge command, a subse- quent command to the same bank cannot be issued until t rp is met. the precharge can be issued coinci- dent with the first coincident clock edge (t2 in figure 23) on an a1 version and with the second clock on an a2 version in figure 23. in the case of a fixed- length burst being executed to completion, a pre- charge command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. the disadvantage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed- length or full-page bursts. figure 21: random write cycles note: each write command may be to any bank. dqm is low. figure 22: write to read note: the write command may be to any bank, and the read command may be to any bank. dqm is low. cas latency = 2 for illustration. don?t care clk dq d in n t2 t1 t3 t0 command address write bank, col n d in a d in x d in m write write write bank, col a bank, col x bank, col m transitioning data don?t care clk dq t2 t1 t3 t0 command address nop write bank, col n d in n d in n + 1 d out b read nop nop bank, col b nop d out b + 1 t4 t5 transitioning data
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 24 ?2002 micron technology, inc. all rights reserved. figure 23: wri te to precharge note: dqm could remain low in this example if the write burst is a fixed length of two. fixed-length or full-page write bursts can be trun- cated with the burst terminate command. when truncating a write burst, the input data applied coin- cident with the burst terminate command will be ignored. the last data written (provided that dqm is low at that time) will be the input data applied one clock previous to the burst terminate command. this is shown in figure 24, where data n is the last desired data element of a longer burst. figure 24: terminating a write burst note: dqm is low. figure 25: precharge command precharge the precharge command shown in figure 25, is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be pre- charged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 are treated as ?don?t care.? once a bank has been pre- charged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. don?t care dqm clk dq t2 t1 t4 t3 t0 command address bank a , col n t5 nop write precharge nop nop d in n d in n + 1 active t rp bank ( a or all) t wr bank a , row dqm dq command address bank a , col n nop write precharge nop nop d in n d in n + 1 active t rp bank ( a or all) t wr bank a , row t6 nop nop t wr @ t clk 15ns t wr = t clk < 15ns transitioning data don?t care transitioning data clk dq t2 t1 t0 command address bank, col n write burst terminate next command d in n (address) (data) don?t care cs# we# cas# ras# cke clk a10 high all banks bank selected a0-a9, a11, a12 ba0, ba1 bank address
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 25 ?2002 micron technology, inc. all rights reserved. power-down power-down occurs if cke is registered low coinci- dent with a nop or command inhibit when no accesses are in progress. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input and output buffers, excluding cke, for maxi- mum power savings while in standby. cke must be held low during power down. the device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. the power-down state is exited by registering a nop or command inhibit and cke high at the desired clock edge (meeting t cks) as shown in figure 26. figure 26: power-down don?t care t ras t rcd t rc all banks idle input buffers gated off exit power-down mode. ( ) ( ) ( ) ( ) ( ) ( ) t cks > t cks command nop active enter power-down mode. nop clk cke ( ) ( ) ( ) ( ) t2 t1 ta1 ta0 ta2 t0
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 26 ?2002 micron technology, inc. all rights reserved. clock suspend the clock suspend mode occurs when a column access/burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deacti- vated, ?freezing? the synchronous logic. for each positive clock edge on which cke is sam- pled low, the next internal positive clock edge is sus- pended. any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the dq pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (see examples in figure 27 and figure 28.) clock suspend mode is exited by registering cke high; the internal clock and related operation will resume on the subsequent posi- tive clock edge. figure 27: clock su spend during write burst note: for this example, burst length = 4 or greater, and dqm is low. burst read/single write the burst read/single write mode is entered by pro- gramming the write burst mode bit (m9) in the mode register to a logic 1. in this mode, all write com- mands result in the access of a single column location (burst of one), regardless of the programmed burst length. read commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (m9 = 0). figure 28: clock suspend during read burst note: for this example, cas latency = 2, burst length = 4 or greater, and dqm is low. don?t care d in command address write bank, col n d in n nop nop clk t2 t1 t4 t3 t5 t0 cke internal clock nop d in n + 1 d in n + 2 transitioning data don?t care clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 cke internal clock nop transitioning data
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 27 ?2002 micron technology, inc. all rights reserved. concurrent auto precharge an access command (read or write) to another bank while an access command with auto precharge enabled is executing is not allowed by sdrams, unless the sdram supports concurrent auto pre- charge. micron sdrams support concurrent auto precharge. four cases where concurrent auto precharge occurs are defined below. read with auto precharge 1. interrupted by a read (with or without auto pre- charge): a read to bank m will interrupt a read on bank n, cas latency later. the precharge to bank n will begin when the read to bank m is registered (figure 29). 2. interrupted by a write (with or without auto pre- charge): a write to bank m will interrupt a read on bank n when registered. dqm should be used two clocks prior to the write command to pre- vent bus contention. the precharge to bank n will begin when the write to bank m is registered (figure 30). figure 29: read with auto precharge interrupted by a read note: dqm is low. figure 30: read with auto pr echarge interrupted by a write note: dqm is high at t2 to prevent d out -a+1 from conten ding with d in -d at t4. don?t care clk dq d out a t2 t1 t4 t3 t6 t5 t0 command read - ap bank n nop nop nop nop d out a + 1 d out d d out d + 1 nop t7 bank n cas latency = 3 (bank m ) bank m address idle nop bank n , col a bank m , col d read - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active read with burst of 4 precharge rp - bank n t rp - bank m cas latency = 3 (bank n ) transitioning data clk dq d out a t2 t1 t4 t3 t6 t5 t0 command nop nop nop nop d in d + 1 d in d d in d + 2 d in d + 3 nop t7 bank n bank m address idle nop dqm bank n , col a bank m , col d write - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active write with burst of 4 write-back rp - bank n t wr - bank m cas latency = 3 (bank n ) read - ap bank n 1 don?t care transitioning data
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 28 ?2002 micron technology, inc. all rights reserved. figure 31: write with auto precharge interrupted by a read note: dqm is low. figure 32: write with auto pr echarge interrupted by a write note: dqm is low. write with auto precharge 1. interrupted by a read (with or without auto pre- charge): a read to bank m will interrupt a write on bank n when registered, with the data-out appearing cas latency later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in reg- istered one clock prior to the read to bank m (figure 31). 2. interrupted by a write (with or without auto pre- charge): a write to bank m will interrupt a write on bank n when registered. the pre- charge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid data write to bank n will be data registered one clock prior to a write to bank m (figure 32). don?t care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in a + 1 d in a nop nop t7 bank n bank m address bank n , col a bank m , col d read - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active read with burst of 4 t t rp - bank m d out d d out d + 1 cas latency = 3 (bank m ) rp - bank n wr - bank n transitioning data don?t care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in d + 1 d in d d in a + 1 d in a + 2 d in a d in d + 2 d in d + 3 nop t7 bank n bank m address nop bank n , col a bank m , col d write - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active write with burst of 4 write-back wr - bank n t rp - bank n t wr - bank m transitioning data
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 29 ?2002 micron technology, inc. all rights reserved. note: 1. cke n is the logic state of cke at clock edge n; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the sd ram immediately prior to clock edge n . 3. command n is the command regist ered at clock edge n , and action n is a result of command n . 4. all states and sequences not sh own are illegal or reserved. 5. exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that t cks is met). 6. exiting self refresh at clock edge n will put the device in th e all banks idle state once t xsr is met. command inhibit or nop commands should be issued on any clock edges occu rring during the t xsr period. a minimum of two nop com- mands must be provided during t xsr period. 7. after exiting clock suspend at clock edge n , the device will resume operation and recognize the next command at clock edge n + 1. table 6: truth table ? cke (notes: 1-4) cke n-1 cke n current state command n action n notes l l power-down x maintain power-down self refresh x maintain self refresh clock suspend x mainta in clock suspend l h power-down command inhibi t or nop exit power-down 5 self refresh command inhibit or nop exit self refresh 6 clock suspend x exit clock suspend 7 h l all banks idle command inhibit or nop power-down entry all banks idle auto refresh self refresh entry reading or writing val id clock suspend entry h h see table 7 on page 30
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 30 ?2002 micron technology, inc. all rights reserved. note: 1. this table ap plies when cke n-1 was high and cke n is high (see table 6 on page 29) and after t xsr has been met (if the previous state was self refresh). 2. this table is bank-specific, except wher e noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in th at state. exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto pr echarge disabled, and has not yet terminated or been terminated. write: a write burst has been initiate d, with auto precharg e disabled, and has not yet terminated or been terminated. 4. the following states must not be interrupted by a comma nd issued to the same bank . command inhibit or nop com- mands, or allowable commands to the other bank should be issued on any clock edge oc curring during these states. allowable commands to the other bank are determined by its current state and truth table 7 on page 30, and according to table 8 on page 32. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating: starts with registration of an active comm and and ends when t rcd is met. once t rcd is met, the bank will be in the row active state. read w/auto precharge enabled: star ts with registration of a read comm and with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto precharge enabled: starts with registratio n of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 5. the following states must not be inte rrupted by any executable command; command inhibit or nop commands must be applied on each positive cl ock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rc is met. once t rc is met, the sdram will be in the all banks idle state. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. once t mrd is met, the sdram will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state. 6. all states and sequences not sh own are illegal or reserved. 7. not bank-specific; requires that all banks are idle. table 7: truth table ? current state bank n , command to bank n notes: 1-6; notes appear below table current state cs# ras# cas# we# command (action) notes any h x x x command inhibi t (nop/continue pr evious operation) l h h h no operation (nop/continue previous operation) idle l l h h active (select and activate row) lllhauto refresh 7 llllload mode register 7 l l h l precharge 11 row active l h l h read (select column and start read burst) 10 l h l l write (select column and start write burst) 10 l l h l precharge (deactivate row in bank or banks) 8 read (auto precharge disabled) l h l h read (select column and start new read burst) 10 l h l l write (select column and start write burst) 10 l l h l precharge (truncate read burst, start precharge) 8 l h h l burst terminate 9 write (auto precharge disabled) l h l h read (select column and start read burst) 10 l h l l write (select column and start new write burst) 10 l l h l precharge (truncate wri te burst, start precharge) 8 l h h l burst terminate 9
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 31 ?2002 micron technology, inc. all rights reserved. 8. may or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. not bank-specific; burst terminate affects the most recent read or write burst, regardless of bank. 10. reads or writes listed in the command (action) column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 11. does not affect the state of the bank and acts as a nop to that bank.
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 32 ?2002 micron technology, inc. all rights reserved. note: 1. this table ap plies when cke n-1 was high and cke n is high (see table 6 on page 29) and after t xsr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except wh ere noted; i.e., the current stat e is for bank n and the com- mands shown are those allowed to be issued to bank m (assu ming that bank m is in such a state that the given com- mand is allowable). exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read w/auto precharge enabled: starts with registration of a read comman d with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto precharge enabled: star ts with registration of a write co mmand with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state. 4. auto refresh, self refresh and load mode register commands may only be issued when a ll banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not sh own are illegal or reserved. 7. reads or writes to bank m listed in the command (actio n) column include reads or writes with auto precharge enabled and reads or writes wi th auto precharge disabled. table 8: truth table ? current st ate bank n, command to bank m notes: 1-6; notes appear below and on next page current state cs# ras# cas# we# command (action) notes any h x x x command inhibit (nop/c ontinue previous operation) l h h h no operation (nop/con tinue previous operation) idle x x x x any command otherwise allowed to bank m row activating, active, or precharging l l h h active (select and activate row) l h l h read (select column and start read burst) 7 l h l l write (select column and start write burst) 7 l l h l precharge read (auto precharge disabled) l l h h active (select and activate row) l h l h read (select column and start new read burst) 7, 10 l h l l write (select column an d start write burst) 7, 11 l l h l precharge 9 write (auto precharge disabled) l l h h active (select and activate row) l h l h read (select column and start read burst) 7, 12 l h l l write (select column an d start new write burst) 7, 13 l l h l precharge 9 read (with auto precharge) l l h h active (select and activate row) l h l h read (select column and start new read burst) 7, 8, 14 l h l l write (select column and start write burst) 7, 8, 15 l l h l precharge 9 write (with auto precharge) l l h h active (select and activate row) l h l h read (select column and start read burst) 7, 8, 16 l h l l write (select co lumn and start new write burst) 7, 8, 17 l l h l precharge 9
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 33 ?2002 micron technology, inc. all rights reserved. 8. concurrent auto precharge: bank n w ill initiate the auto precharge comman d when its burst has been interrupted by bank m?s burst. 9. burst in bank n continues as initiated. 10. for a read without auto precharge interrupted by a read (wi th or without auto precharge), the read to bank m will interrupt the read on bank n, cas latency later (figure 12). 11. for a read without auto precharge interrupted by a write (w ith or without auto precharge), the write to bank m will interrupt the read on bank n when registered (figure 18 and figure 19). dqm should be used one clock prior to the write command to prevent bus contention. 12. for a write without auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when regist ered (figure 22), with the data-out appearing cas latency later. the last valid write to bank n will be data-in registered one clock prior to the read to bank m. 13. for a write without auto precharge interrupted by a write (with or without auto precharge), the write to bank will interrupt the write on bank n wh en registered (figure 20). the last valid writ e to bank n will be data-in registered one clock prior to the read to bank m. 14. for a read with auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the read on bank n, cas latency later. the prechar ge to bank n will begin when the read to bank m is reg- istered (figure 28). 15. for a read with auto precharge interrupted by a write (wi th or without auto precharge), the write to bank m will interrupt the read on bank n when registe red. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin wh en the write to bank m is registered (figure 29). 16. for a write with auto precha rge interrupted by a read (wi th or without auto precharg e), the read to bank m will interrupt the write on bank n when re gistered, with the data-out appearing cas latency later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write bank n will be data-in registered one clock pr ior to the read to bank m (figure 30). 17. for a write with auto precha rge interrupted by a write (with or without auto precharge), the wr ite to bank m inter- rupt the write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid writ e to bank n will be data regi stered one clock to the write to bank m (figure 31).
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 34 ?2002 micron technology, inc. all rights reserved. absolute maximum ratings voltage on v dd /v dd q supply relative to v ss (3.3v) . . . . . . . . . . . . . . . . . -1v to +4.6v relative to v ss (3.0v) . . . . . . . . . . . . . . . . . -1v to +4.6v relative to v ss (2.5v) . . . . . . . . . . . . . . . . . -1v to +4.6v voltage on inputs, nc or i/o pins relative to v ss (3.3v) . . . . . . . . . . . . . . . . . -1v to +4.6v relative to v ss (3.0v) . . . . . . . . . . . . . . . . . -1v to +4.6v relative to v ss (2.5v) . . . . . . . . . . . . . . . . . -1v to +4.6v operating temperature t a (commercial) . . . . . . . . . . . . . . . . . . . 0c to +70c t a (industrial) . . . . . . . . . . . . . . . . . . . . .-40c to +85c t a (extended) . . . . . . . . . . . . . . . . . . . . . -25c to +75c storage temperature (plastic) . . . . . . -55c to +150c stresses greater than those listed may cause perma- nent damage to the device. th is is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. table 9: dc electrical characteristi cs and operating cond itions (lc version) notes: 1,5, 6; notes appear on page 39; v dd = +3.3v 0.3v, v dd q = +3.3v 0.3v parameter/condition symbol min max units notes supply voltage v dd 33.6v i/o supply voltage v dd q33.6v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 22 input low voltage: logic 0; all inputs v il -0.3 0.8 v 22 data output high voltage: logic 1; all inputs v oh 2.4 ? v data output low voltage: logic 0; all inputs v ol ?0.4v input leakage current: any input 0v vin v dd (all other pins not under test = 0v) i i -5 5 a output leakage current: dqs are disabled; 0v vout v dd qi oz -5 5 a table 10: dc electrical characteristi cs and operating cond itions (g version) notes 1,5, 6; notes appear on page 39; v dd = +3.0v 0.3v, v dd q = +3.0v 0.3v parameter/condition symbol min max units notes supply voltage v dd 2.7 3.3 v i/o supply voltage v dd q2.73.3 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 22 input low voltage: logic 0; all inputs v il -0.3 0.8 v 22 data output high voltage: logic 1; all inputs v oh 2.4 ? v data output low voltage: logic 0; all inputs v ol ?0.4v input leakage current: any input 0v vin v dd (all other pins not under test = 0v) i i -5 5 a output leakage current: dqs are disabled; 0v vout v dd qi oz -5 5 a
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 35 ?2002 micron technology, inc. all rights reserved. table 11: dc electrical characteristi cs and operating cond itions (v version) notes: 1,5, 6; notes appear on page 39; v dd = 2.5 0.2v, v dd q = +2.5v 0.2v or +1.8v 0.1v parameter/condition symbol min max units notes supply voltage v dd 2.3 2.7 v i/o supply voltage v dd q1.7 2.7 v input high voltage: logic 1; all inputs v ih 0.8 * v dd qv dd q + 0.3 v22 input low voltage: logic 0; all inputs v il -0.3 +0.55 v 22 data output high voltage: logic 1; all inputs v oh v dd q - 0.2 ? v data output low voltage: logic 0; all inputs v ol ?0.2v input leakage current: any input 0v vin v dd (all other pins not under test = 0v) i i -5 5 a output leakage current: dqs are disabled; 0v vout v dd qi oz -5 5 a table 12: capacitance - vfbga note 2; notes appear on page 39 parameter symbol min max units notes input capacitance: clk c i1 1.5 4.0 pf 28 input capacitance: all other input-only pins c i2 1.5 4.0 pf 29 input/output capacitance: dqs c io 3.0 6.0 pf 30 table 13: capacitance - tsop note 2; notes appear on page 39 parameter symbol min max units notes input capacitance: clk c i1 2.5 4.0 pf 28 input capacitance: all other input-only pins c i2 2.5 4.0 pf 29 input/output capacitance: dqs c io 4.0 6.0 pf 30
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 36 ?2002 micron technology, inc. all rights reserved. table 14: electrical characteristics an d recommended ac operating conditions notes: 5, 6, 8, 9, 11; notes appear on page 39 ac characteristics parameter symbol -75 -8 -10 units notes min max min max min max access time from clk (pos. edge) cl = 3 t ac (3) 5.4 77ns32 cl = 2 t ac (2) 6 88ns cl = 1 t ac (1) ? 19 22 ns address hold time t ah 0.8 11ns address setup time t as 1.5 2.5 2.5 ns clk high-level width t ch 3.0 33ns clk low-level width t cl 3.0 33ns clock cycle time cl = 3 t ck (3) 7.5 89.6ns23 cl = 2 t ck (2) 9.6 9.6 12 ns 23 cl = 1 t ck (1) - 20 25 ns 23 cke hold time t ckh 0.8 11ns cke setup time t cks 1.5 2.5 2.5 ns cs#, ras#, cas#, we#, dqm hold time t cmh 0.8 11ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 2.5 2.5 ns data-in hold time t dh 0.8 11ns data-in setup time t ds 1.5 2.5 2.5 ns data-out high-impedance time cl = 3 t hz (3) 5.4 77ns10 cl = 2 t hz (2) 6 88ns10 cl = 1 t hz (1) - 19 22 ns 10 data-out low-impedance time t lz 1 11ns data-out hold time (load) t oh 2.5 2.5 2.5 ns data-out hold time (no load) t oh n 1.8 1.8 1.8 ns 27 active to precharge command t ras 44 120,000 48 120,000 50 120,000 ns active to active command period t rc 66 80 100 ns active to read or write delay t rcd 19 19 20 ns refresh period (8,192 rows) t ref 64 64 64 ms auto refresh command period t rfc 66 80 100 ns precharge command period t rp 19 19 20 ns active bank a to active bank b command t rrd 15 16 20 ns transition time t t 0.3 1.2 0.5 1.2 0.5 1.2 ns 7 write recovery time auto precharge mode t wr (a) 1 clk + 7.5ns 1 clk +7ns 1 clk +5ns ?24 manual precharge mode t wr (m) 15 15 15 ns 25 exit self refresh to active command t xsr 75 80 100 ns 20
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 37 ?2002 micron technology, inc. all rights reserved. table 15: ac function al characteristics notes: 5, 6, 7, 8, 9, 11; notes appear on page 39 parameter symbol -75 -8 -10 units notes read/write command to read/write command t ccd 111 t ck 17 cke to clock disable or power-down entry mode t cked 111 t ck 14 cke to clock enable or power-down exit setup mode t ped 111 t ck 14 dqm to input data delay t dqd 000 t ck 17 dqm to data mask during writes t dqm 000 t ck 17 dqm to data high-impedance during reads t dqz 222 t ck 17 write command to input data delay t dwd 000 t ck 17 data-in to active command t dal 555 t ck 15, 21 data-in to precharge command t dpl 222 t ck 16, 21 last data-in to burst stop command t bdl 111 t ck 17 last data-in to ne w read/write command t cdl 111 t ck 17 last data-in to precharge command t rdl 222 t ck 16, 21 load mode register command to active or refresh command t mrd 222 t ck 26 data-out to high-imp edance from precharge command cl = 3 t roh(3) 333 t ck 17 cl = 2 t roh(2) 222 t ck 17 cl = 1 t roh(1) -11 t ck 17
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 38 ?2002 micron technology, inc. all rights reserved. table 16: i dd specifications and condi tions - lc, g, v versions (notes: 1, 6, 11, 13, 28; notes appear on page 39 max parameter/condition symbol -75 -8 -10 units notes operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd1 85 75 70 ma 18, 19 standby current: power-down mode; all banks idle; cke = low i dd2 500 500 500 a 12, 30 standby current: active mode; cke = high; cs# = high; all banks active after t rcd met; no accesses in progress i dd3 25 25 25 ma 19 operating current: burst mode; page burst; read or write; all banks active i dd4 115 105 95 ma 18, 19 auto refresh current cke = high; cs# = high t rfc = t rfc (min) i dd5 175 165 155 ma 3, 12, 18, 19, 29, 30 t rfc = 7.8s i dd6 2.5 2.5 2.5 ma table 17: i dd 7 self refresh current options - lc, g, v versions (notes: 4 appears on page 39) lc, g, v versions temperature compensated self refresh parameter/condition max temperature -75/-8/-10 units self refresh current: cke < 0.2v 85oc 750 a 45oc 400 a
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 39 ?2002 micron technology, inc. all rights reserved. notes 1. all voltages are referenced to vss 2. this parameter is sampled; f = 1 mhz, t a = 25c, 1.4v bias, 200mv swing, v dd = +3.3v, v dd q =+3.3v for the "lc" version; f = 1 mhz, t a = 25c; 1.4v bias, 200mv swing, v dd = +3.0v, v dd q =+3.0v for the "g" version; and f = 1 mhz, t a = 25c; 0.9v bias, 200mv swing, v dd = +2.5v, v dd q =+2.5v for the "v" version. 3. i dd is dependent on output loading and cycle rates. specified values are obtained with mini- mum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full operational temperature range is ensured ( t a = commercial, it or xt). 6. an initial pause of 100s is required after power- up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be powered up simultaneously. v ss and v ss q must be at same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specifi- cation, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a mono- tonic manner. 9. outputs measured at 0.9v with equivalent load: 10. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests use established values for v il and v ih , with timing referenced to v ih /2 crossover point. if the input transition time is longer than 1ns, then the timing is referenced at v il ( max ) and v ih ( min ) and no longer at the v ih /2 crossover point. 12. other input signals are allowed to transition no more than once every two clocks and are other- wise at valid v ih or v il levels. 13. i dd specifications are tested after the device is properly initialized. 14. timing actually specified by t cks; clock(s) speci- fied as a reference only at minimum cycle rate. 15. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec function- ality and are not dependent on any timing param- eter. 18. the i dd current will increase or decrease propor- tionally according to the amount of frequency alteration for the test condition. 19. address transitions aver age one transition every two clocks. 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 133mhz for -75, t ck = 125mhz for -8, and t ck = 104mhz for -10. 22. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il under- shoot: v il (min) = -2v for a pulse width 3ns. 23. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, includ- ing t wr, and precharge commands). cke may be used to reduce the data rate. 24. auto precharge mode only. the precharge timing budget ( t rp) begins at 5.4ns for -8 after the first clock delay, after the last write is executed. 25. precharge mode only. 26. jedec and pc100 specify three clocks. 27. parameter guaranteed by design. 28. for -75, cl = 2 and t ck = 8ns; for -8, cl = 2 and t ck = 9.6ns; for -10, cl = 3 and t ck = 9.6ns. 29. cke is high during refresh command period t rfc (min) else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value. 30. specified with i/o?s in steady state condition. 31. measured at nominal value at 25c. 32. for -75 only, if v dd q = 1.8 0.1v, t ac (3)=- 6ns. q 30pf
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 40 ?2002 micron technology, inc. all rights reserved. figure 33: initialize and load mode register 1,2 note: 1. the two auto refresh commands at t9 and t19 may be ap plied before either load mo de register (lmr) command. 2. pre = precharge command, lmr = load mode register command, ar = auto refres h command, act = active command, ra = row address, ba = bank address. 3. optional refresh command. 4. the load mode register for bo th mr/emr and 2 auto refresh commands can be in any order. ho wever, all must occur prior to an active command. 5. device timing is -1 0 with 104 mhz clock. for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. cke ba0, ba1 load extended mode register load mode register t cks power-up: v dd and clk stable t = 100s t ckh ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dqml/u (x16) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq high-z a0-a9, a11, a12 ra a10 ra all banks clk t ck command 6 lmr 4 nop pre 3 lmr 4 ar 4 ar 4 act 4 t cmh t cms ba0 = l, ba1 = h t as t ah t as t ah ba0 = l, ba1 = l ( ) ( ) ( ) ( ) code code t as t ah code code ( ) ( ) ( ) ( ) pre all banks t as t ah ( ) ( ) ( ) ( ) t0 t1 t3 t5 t7 t9 t19 t29 ( ) ( ) ( ) ( ) don?t care ba ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp t mrd t mrd t rp t rfc t rfc ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 41 ?2002 micron technology, inc. all rights reserved. figure 34: power-down mode 1 note: 1. violating refresh requirements during po wer-down may result in a loss of data. for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. t ch t cl t ck two clock cycles cke clk dq all banks idle, enter power-down mode precharge all active banks input buffers gated off while in power-down mode exit power-down mode ( ) ( ) ( ) ( ) don?t care undefined t cks t cks command t cmh t cms precharge nop nop active nop ( ) ( ) ( ) ( ) all banks idle ba0, ba1 bank bank(s) ( ) ( ) ( ) ( ) high-z t ah t as t ckh t cks dqm/ dqml, dqmu ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) a0?a9, a11, a12 row ( ) ( ) ( ) ( ) all banks single bank a10 row ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 tn + 2 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 42 ?2002 micron technology, inc. all rights reserved. figure 35: clock suspend mode note: 1. for this example, the burst length = 2, the ca s latency = 3, and auto precharge is disabled. 2. a9, a11, and a12= ?don?t care.? for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. t ch t cl t ck t ac t lz dqm/ dqml, dqmu clk a0-a9, a11, a12 dq ba0, ba1 a10 t oh d out m t ah t as t ah t as t ah t as bank t dh d out e t ac t hz d out m + 1 command t cmh t cms nop nop nop nop nop read write don?t care undefined cke t cks t ckh bank column m t ds d out + 1 nop t ckh t cks t cmh t cms 2 column e 2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 43 ?2002 micron technology, inc. all rights reserved. figure 36: auto refresh mode note: 1. each auto refresh command performs a refresh cy cle. back-to-back comma nds are not required. for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. t ch t cl t ck cke clk dq t rfc rfc ( ) ( ) ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) command t cmh t cms nop nop ( ) ( ) ( ) ( ) bank active auto refresh ( ) ( ) ( ) ( ) nop nop precharge precharge all active banks auto refresh t high-z ba0, ba1 bank(s) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t ah t as t ckh t cks ( ) ( ) nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dqm / dqml, dqmu a0?a9, a11, a12 row ( ) ( ) ( ) ( ) all banks single bank a10 row ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) don?t care t0 t1 t2 tn + 1 to + 1
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 44 ?2002 micron technology, inc. all rights reserved. figure 37: self refresh mode note: 1. no maximum time li mit for self refresh. t ras (max) only applies to non-self refresh mode. 2. t xsr requires a minimum of two clocks regardless of frequency or timing. 3. as a general rule, any time self refres h is exited, the dram may not re-enter th e self refresh mode until all rows have been refreshed via the auto refresh co mmand at the distributed refresh rate, t ref, or faster. however, the following exception is allowed. self refresh mode may be re-entered any time after exiting, if th e following conditions are all met: a.) the dram has been in the self refresh mode for a minimum of 64ms prior to exiting. b.) t xsr has not been violated. c.) at least two auto refresh commands are performed during each 15.625us interval while the dram remains out of the self refresh mode. for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. t ch t cl t ck t rp cke clk dq enter self refresh mode 3 precharge all active banks t xsr 2 clk stable prior to exiting self refresh mode exit self refresh mode 3 (restart refresh time base) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) don?t care command t cmh t cms auto refresh precharge nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ba0, ba1 bank(s) ( ) ( ) ( ) ( ) high-z t cks ah as auto refresh > t ras 1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t ckh t cks dqm/ dqml, dqmh ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t t t cks a0-a12 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) all banks single bank a10 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 to + 1 to + 2 ( ) ( ) ( ) ( )
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 45 ?2002 micron technology, inc. all rights reserved. figure 38: read ? wi thout auto precharge1 note: 1. for this example, the burst length = 4, the cas latency = 2, and the read burst is followed by a ?manual? precharge. 2. a9, a11, and a12= ?don?t care.? for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. all banks t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc dqm/ dqml, dqmu cke clk a0-a9, a11, a12 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank bank row row bank t hz t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms precharge nop nop nop active nop read nop active disable auto precharge single bank don?t care undefined t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 46 ?2002 micron technology, inc. all rights reserved. figure 39: read ? with auto precharge 1 note: 1. for this example, the burst length = 4, the cas latency = 2. 2. a9, a11, and a12= ?don?t care.? for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. enable auto precharge t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc dqm/ dqml, dqmu cke clk a0-a9, a11, a12 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank row row bank don?t care undefined t hz t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms nop nop nop active nop read nop active nop t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 47 ?2002 micron technology, inc. all rights reserved. figure 40: single read ? without auto precharge 1 note: 1. for this example, the burst length = 4, the cas latency = 2, and the read burst is followed by a ?manual? precharge. 2. a9, a11, and a12= ?don?t care.? 3. precharge comman d not allowed or t ras would be violated. for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. all banks t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc dqm/ dqml, dqmu cke clk a0-a9, a11, a12 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank bank row row bank t hz t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms precharge nop nop nop active nop read nop active disable auto precharge single bank don?t care undefined t ckh t cks column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 48 ?2002 micron technology, inc. all rights reserved. figure 41: single read ? with auto precharge 1 note: 1. for this example, the burst length = 4, the cas latency = 2, and the read burst is followed by a ?manual? precharge. 2. a9, a11, and a12= ?don?t care.? 3. precharge comman d not allowed or t ras would be violated. for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. all banks t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row bank bank(s) bank row row bank t hz t cmh t cms nop nop nop precharge active nop read active nop disable auto precharge single banks don?t care undefined column m 3 t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 dqm / dqml, dqmu cke clk a0-a9, a11,a12 dq ba0, ba1 a10 command 2 2
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 49 ?2002 micron technology, inc. all rights reserved. figure 42: alternating bank read accesses 1 note: 1. for this example, the burst leng th = 4, the cas latency = 2. 2. a9, a11, and a12= ?don?t care.? for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. enable auto precharge t ch t cl t ck t ac t lz dqm/ dqml, dqmu clk a0-a9, a11, a12 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ah t as row row row row don?t care undefined t oh d out m + 3 t ac t oh t ac t oh t ac d out m + 2 d out m + 1 command t cmh t cms nop nop active nop read nop active t oh d out b t ac t ac read enable auto precharge row active row bank 0 bank 0 bank 3 bank 3 bank 0 cke t ckh t cks column m 2 column b 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t rcd - bank 0 cas latency - bank 0 t rcd - bank 1 cas latency - bank 1 t t rc - bank 0 rrd
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 50 ?2002 micron technology, inc. all rights reserved. figure 43: read ? full-page burst 1 note: 1. for this example, the cas latency = 2. 2. a9, a11, and a12= ?don?t care.? 3. page left open; no t rp. for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. t ch t cl t ck t ac t lz t rcd cas latency dqm/ dqml, dqmh cke clk a0-a9, a11, a12 dq ba0, ba1 a10 t oh d out m t cmh t cms t ah t as t ah t as t ac t oh d out m +1 row row t hz t ac t oh d out m +1 t ac t oh d out m +2 t ac t oh d out m -1 t ac t oh dout m full-page burst does not self-terminate. can use burst terminate command. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed 512 locations within same row don?t care undefined command t cmh t cms nop nop nop active nop read nop burst term nop nop ( ) ( ) ( ) ( ) nop ( ) ( ) ( ) ( ) t ah t as bank ( ) ( ) ( ) ( ) bank t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) column m 2 3 t0 t1 t2 t4 t3 t5 t6 tn + 1 tn + 2 tn + 3 tn + 4
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 51 ?2002 micron technology, inc. all rights reserved. figure 44: read ? dqm operation 1 note: 1. for this example, the cas latency = 2. 2. a9, a11, and a12= ?don?t care.? for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. t ch t cl t ck t rcd cas latency dqm/ dqml, dqmu cke clk a0-a9, a11, a12 dq ba0, ba1 a10 t cms row bank row bank don?t care undefined t ac lz d out m t oh d out m + 3 d out m + 2 t t hz lz t t cmh command nop nop nop active nop read nop nop nop t hz t ac t oh t ac t oh t ah t as t cms t cmh t ah t as t ah t as t ckh t cks enable auto precharge disable auto precharge column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 52 ?2002 micron technology, inc. all rights reserved. figure 45: write ? wi thout auto precharge 1 note: 1. for this example, the burst length = 4, and th e write burst is followed by a ?manual? precharge. 2. 15ns is required between and the precharge command, re gardless of frequency. 3. a9, a11, and a12= ?don?t care.? for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. disable auto precharge t ch t cl t ck t rp t ras t rcd t rc dqm/ dqml, dqmu cke clk a0?a9, a11, a12 dq ba0, ba1 a10 t cmh t cms t ah t as row bank bank row bank t don?t care d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop nop active nop write precharge t ah t as t ah t as t dh t ds t dh t ds t dh t ds single bank t ckh t cks column m 2 3 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 row bank row active nop wr nop all banks
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 53 ?2002 micron technology, inc. all rights reserved. figure 46: write ? with auto precharge 1 note: 1. for this example, the burst length = 4. 2. a9, a11, and a12= ?don?t care.? for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. enable auto precharge t ch t cl t ck t rp t ras t rcd t rc dqm/ dqml, dqmu cke clk a0-a9, a11, a12 dq ba0, ba1 a10 t cmh t cms t ah t as row row bank bank row row bank t wr don?t care d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop nop active nop write nop active t ah t as t ah t as t dh t ds t dh t ds t dh t ds t ckh t cks nop nop column m 2 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 54 ?2002 micron technology, inc. all rights reserved. figure 47: single write ? without auto precharge 1 note: 1. for this example, the burst length = 1, and th e write burst is followed by a ?manual? precharge. 2. 15ns is required between and the precharge command, regardless of frequency. 3. a9, a11, and a12= ?don?t care.? 4. precharge command not allowed else t ras would be violated. for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. disable auto precharge all banks t ch t cl t ck t rp t ras t rcd t rc dqm / dqml, dqmu cke clk a0-a9, a11 dq ba0, ba1 a10 t cmh t cms t ah t as row bank bank bank row row bank t wr d in m t dh t ds command t cmh t cms nop 2 nop 2 precharge active nop write active nop nop t ah t as t ah t as single bank t ckh t cks column m 3 4 t0 t1 t2 t4 t3 t5 t6 t7 t8 don?t care
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 55 ?2002 micron technology, inc. all rights reserved. figure 48: single write ? with auto precharge 1 note: 1. for this example, the burst length = 1, and th e write burst is followed by a ?manual? precharge. 2. 15ns is required between and the precharge command, regardless of frequency. 3. a9, a11, and a12= ?don?t care.? 4. write command not allowed else t ras would be violated. for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. enable auto precharge t ch t cl t ck t rp t ras t rcd t rc dqm/ dqml, dqmu cke ck a0-a9, a11, a12 dq ba0, ba1 a10 t cmh t cms t ah t as row row bank bank row row bank t wr 4 d in m command t cmh t cms nop 2 nop 2 nop active nop 2 write nop active t ah t as t ah t as t dh t ds t ckh t cks nop nop column m 3 t0 t1 t2 t4 t3 t5 t6 t7 t8 t9 don?t care
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 56 ?2002 micron technology, inc. all rights reserved. figure 49: alternating bank write accesses 1 note: 1. for this example, the burst length = 4. 2. a9, a11, and a12= ?don?t care.? for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. t ch t cl t ck clk dq don?t care d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 command t cmh t cms nop nop active nop write nop nop active t dh t ds t dh t ds t dh t ds active write d in b t dh t ds d in b + 1 d in b + 3 t dh t ds t dh t ds dqm/ dqml, dqmu a0-a9, a11, a12 ba0, ba1 a10 t cmh t cms t ah t as t ah t as t ah t as row row row row row row bank 0 bank 0 bank 1 bank 0 bank 1 cke t ckh t cks d in b + 2 t dh t ds column b 3 column m 3 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t t rcd - bank 0 t wr - bank 0 wr - bank 1 t rcd - bank 1 t t rc - bank 0 rrd t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 57 ?2002 micron technology, inc. all rights reserved. figure 50: write ? full-page burst 1 note: 1. a9, a11, and a12= ?don?t care.? 2. t wr must be satisfied pr ior to precharge command. 3. page left open; no t rp. for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. t ch t cl t ck t rcd dqm/ dqml, dqmh cke clk a0?a9, a11, a12 ba0, ba1 a10 t cms t ah t as t ah t as row row full-page burst does not self-terminate. can use burst terminate command to stop. 2, 3 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed don?t care command t cmh t cms nop nop nop active nop write burst term nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq d in m t dh t ds d in m + 1 d in m + 2 d in m + 3 t dh t ds t dh t ds t dh t ds d in m - 1 t dh t ds t ah t as bank ( ) ( ) ( ) ( ) bank t cmh t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 512 locations within same row column m 1 t0 t1 t2 t3 t4 t5 tn + 1 tn + 2 tn + 3
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 58 ?2002 micron technology, inc. all rights reserved. figure 51: write ? dqm operation 1 note: 1. for this example, the burst length = 4. 2. a9, a11, and a12= ?don?t care.? for actual values, see table 14, electr ical characteristics and recommended ac operating conditions, on page 36. t ch t cl t ck t rcd dqm/ dqml, dqmu cke clk a0-a9, a11, a12 dq ba0, ba1 a10 t cms t ah t as row bank row bank enable auto precharge d in m + 3 t dh t ds d in m d in m + 2 t cmh command nop nop nop active nop write nop nop don?t care t cms t cmh t dh t ds t dh t ds t ah t as t ah t as disable auto precharge t ckh t cks column m 2 t0 t1 t2 t3 t4 t5 t6 t7
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 59 ?2002 micron technology, inc. all rights reserved. figure 52: 54-pin plastic tsopii (400 mil) note: 1. all dimensions in millimeters or typical where noted. 2. package width and length do not in clude mold protrusion; allowable mold protrusion is 0.25mm per side. see detail a 0.80 typ 0.71 10.16 0.08 0.50 0.10 pin #1 id detail a 22.22 0.08 0.375 0.075 1.2 max 0.10 0.25 11.76 0.20 0.80 typ 0.15 +0.03 -0.02 0.10 +0.10 -0.05 gage plane plastic package material: epoxy novolac lead finish: tin/lead plate package width and length do not include mold protrusion. allowable protrusion is 0.25 per side.
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 60 ?2002 micron technology, inc. all rights reserved. figure 53: vfbga 54-ball, 8mm x 14mm note: all dimensions ar e in millimeters. ball a1 id 1.00 max mold compound: epoxy novolac substrate material: plastic laminate solder ball material: 62% sn, 36% pb, 2% ag or 96.5% sn, 3%ag, 0.5% cu solder mask defined ball pads: ? 0.40 14.00 0.10 ball a1 ball a9 ball a1 id 0.80 typ 0.80 typ 7.00 0.05 8.00 0.10 4.00 0.05 3.20 0.05 3.20 0.05 0.65 0.05 seating plane c 6.40 6.40 0.10 c 54x ?0.45 solder ball diameter refers to post reflow condition. the pre- reflow diameter is ?0.42 c l c l
256mb: x16 mobile sdram preliminary 09005aef80737ef7 micron technology, inc., reserves the right to change products or specifications without notice. 256mbx16_2.fm - rev. e 4/04 en 61 ?2002 micron technology, inc. all rights reserved. ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www .micron.com, customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks and/or service marks of micron technology, inc. all other trademarks are the property of their respective owners. figure 54: vfbga 54-ball, 11mm x 8mm note: all dimensions ar e in millimeters. data sheet designation preliminary: this data sheet contains initial charac- terization limits that are subject to change upon full characterization of production devices. ball a1 id substrate: plastic laminate mold compound: epoxy novolac solder ball material: 62% sn, 36% pb, 2% ag or 96.5% sn, 3% ag, 0.5% cu ball pad: ? 0.40 solder mask defined seating plane ball a9 solder ball diameter refers to post reflow condition. the pre- reflow diameter is ? 0.42. 0.10 c c 0.65 0.05 0.80 typ 6.40 1.00 max 3.20 0.05 4.00 0.05 ball a1 id ball a1 0.80 typ 5.50 0.05 3.20 0.05 11.00 0.10 6.40 54x ? 0.45 0.05 c l c l 8.00 0.10

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